CMOS/NMOS-clocked chip designs use two or more symmetric non-overlapping clock phases to perform a given logic function. This type of clock is used in the Intel 80286 and 80386 microprocessors. Four clocks, PH1, PH1I, PH2, PH2I are distributed in the chip. PH1 and PH2 are traditional NMOS nonoverlapping clocks with equal duty cycles. PH1I and PH2I are the PMOS analogs to PH1 and PH2 and are exactly inversions of PH1 and PH2, respectively. Successive PH1 and PH2 assertions form a microcycle that is 62.5 nanoseconds when the chip is operated at 16-MHz frequency.
In the prior art, the method of generating two nonoverlapped clocks is for the user system to provide an input clock frequency that is exactly twice the frequency of the desired internal clock frequency. Thus, to generate an internal PH1 and PH2 clock frequency of 20 MHz, a 40-MHz-external-clock frequency is applied as input to the chip. This input frequency is then divided by a factor of two to generate a 20-MHz, 50% duty-cycle clock that is used as an input to a waveshaping circuit which generates two symmetric nonoverlapping clocks.
A typical two-phase, symmetric, nonoverlapped clock generator is shown in FIG. 1. The clock input (10) is provided to a level shifter and clock buffer (12). The output (14) of the buffer is provided to a divide-by-two circuit (16), which divides the frequency of clock (10) down to a positive-going clock level (18), and a negative-going clock level (20). These clock levels are input to a clock driver waveshaper and buffer (22) that generates the PH1 and PH2 clock lines (24, 26) and the inversions of these lines PH1I and PH2I (28, 30) from the clock levels (18, 20).
This method of generating two symmetric non-overlapping clocks is preferable to having users externally supply to the chip the two non-overlapping to be buffered or used by the chip directly. This is because it is very difficult to generate symmetric, non-overlapping clocks externally. Board impedance, board signal routing, and clock-chip driving variability combine to make externally generated non-overlapping clocks not very cost effective.
The prior art circuit of FIG. 1 has a major disadvantage. A large clock skew, that is clock delay, from the transistion of the external clock input (10) to the generated transistions of the internal PH1 and PH2 clocks (66, 68) occurs due to the buffering and intermediate logic, notably the divide-by-two circuit that is in the critical path to generating PH1 and PH2. This clock delay between the internally generated clock and the external system clock makes it difficult to synchronize logic chip outputs that are activated by using the internal PH1, PH2 clocks, with the external system clock.
It is an object of the present invention to provide an improved symmetric, non-overlapping clock generator that minimizes the time delay between the external system clock and the internally generated clock signals.